IBM and Samsung have announced a new semiconductor manufacturing design architecture they’re calling Vertical-Transport Nanosheet Field Effect Transistors (VTFET for short).
The worldwide semiconductor chip scarcity has caused widespread concern as businesses in different industries have turned to backup plans. However, it has driven a considerable increase in the amount of money spent on research and development in order to identify new answers.
In compared to scaled finFET transistors, IBM and Samsung Electronics have announced a development that defies standard semiconductor architecture and intends to lower chip energy usage by 85 percent or double performance.
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IBM and Samsung’s new VTFET design prototype, developed by a combined team of researchers at the Albany Nanotech Complex, successfully executes transistors constructed vertically on the surface of a chip. Because transistors have traditionally been designed horizontally to lie flat on a semiconductor’s surface, an exponential number of transistors can be packed onto a chip, removing density and energy efficiency limitations.
As chip designers seek to pack more transistors into a fixed space, the VTFET technique overcomes several performance barriers and difficulties. It also affects transistor contact points, allowing for more current flow while wasting less energy. In comparison to scaled finFET alternatives, the new design intends to produce a two-fold gain in performance or an 85 percent reduction in energy utilization.
Meanwhile, Samsung and IBM aren’t the only ones working on this technology. Intel, the world’s largest chipmaker, is also investigating chips with transistors layered on top of each other to save space, shorten interconnect lengths, and save energy.
These processors are projected to be completed by 2024, using Intel’s new “Intel 20A” node with RibbonFET transistors.
